The invention relates to a bistable logic circuit using field effect transistors with a low voltage threshold and a storage device incorporating such a circuit.
Static random access memories comprise matrices of active elements with two stable states, one corresponding to the state "0" and the other to the state "1". The addressing of each element, which is consequently a bistable circuit for reading or writing, takes place by the selection of the row and the column at the intersection of which the addressed element is located.
The quality and advantage of each type of memory essentially depends on the stability and reduced size of each element. It is known to produce these memories in "MESFET" technology on gallium arsenide (GaAs).
However, the high density of the memories requires a logic circuit technology with a very low consumption, which eliminates a logic with buffer store elements or buffered FET logic with "normally conductive MESFET" transistors, which is the only one whose technology has proved itself. In addition, there are logics comprising field effect transistors and Schottky diodes of the Schottky diode-FET logic type and high performance logics based on junction field effect transistors or Enhanced Junction FET Logics or "E.J.F.E.T.L", which indeed comply with the consumption criteria, but their technologies are too complex to be used for obtaining large-scale integration circuits (LSI).
European Patent Application No. 0 021 858 describes a new logic based on MESFET transistors having a very low negative threshold voltage, which meets various criteria of large-scale integration circuits, namely low consumption, simple technology and permitting a good tolerance in connection with manufacture.